In the formation of fine-line MOS devices, a recurring and severe problem as the devices become smaller is hot carrier instability (HCI). This problem is related to the shorter channels of the smaller devices, such as when the channel length is 1 micron (.mu.m) or smaller, and occurs due to high electrical fields between the source and the drain, particularly near the drain that cause carriers, either electrons or holes, to be injected into the gate or substrate. The injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance, thus, HCI may also stand for hot carrier injection.
The effect of the high-charge levels in the thin gate dielectric is to shift the MOS field effect transistor (FET) device threshold, which makes it difficult or impossible for the FET device to operate correctly. HCI into gate insulators is a universal problem for small geometry FETs (channel lengths less than or equal to 1 .mu.m), since most hot carriers are trapped within approximately 100 .ANG. of the semiconductor surface.
This problem has been addressed by attempting to reduce the strength of the electric field near the source and the drain regions. One approach concerns using a graded drain structure, or graded source/drain (GSD). For instance, in an n-channel device, a heavily doped drain of phosphorous or arsenic surrounded by a lighter doping of phosphorus is used to gradually extend the drain region into the channel region to reduce the electric field strength right at the drain. However, this approach can be undesirable in that it causes larger overlap capacitance with the gate, larger lateral diffusion and channel shortening. Typically, merely the deeper junction of the drain produces more disadvantageous short channel effects, such as an abrupt drop off of threshold voltage with the effective channel length (L.sub.eff).
Further, the drain is preferred to be shallow and laterally graded as to profile as well as concentration. That is, it is desired for the drain profile to have a gradual decrease in surface concentration from the n.sup.+ regions to the channel region. Less desirable is the profile shape where the source/drain regions exhibit similar lateral grading but with deeper vertical junctions. With deeper junctions, there is a wider subsurface depletion effect and it is easier for the field lines to go from the drain to the source, which causes "punchthrough current" problems and shorts out the device.
A known alternative to the graded source/drain structure is the use of lightly doped drains (LDDs). LDDs consist of a lightly doped source/drain region that is driven just under the gate region, while the heavily doped drain region is laterally displaced away from the gate by used of a sidewall spacer on the gate. LDDs are advantageous because they do not have problems with excess lateral or vertical impurity diffusion. However, the process for making LDDs can be complex, and typically requires the formation of a sidewall spacer on the gate to provide the exact horizontal and/or lateral displacement of the lightly and heavily doped drain sections. that is, in LDDs, the n.sup.- portion of the source/drain region is aligned to the polysilicon gate edge, and the n.sup.+ portion of the source/drain region is aligned to a spacer edge.
Another alternative to these structures is a double diffused drain (DDD). This feature is similar to the graded source/drain discussed above, except that in this case, arsenic and phosphorus are implanted together, or are introduced into the same area, and are diffused together to form the source/drain structure. That is, both the n.sup.- and n.sup.+ portions of the source/drain regions are aligned to the polysilicon gate edge. The process for making DDDs is very simple compared to that for making graded source/drains or LDDs in that the impurity introduction is performed essentially all at one time, and the anneal for both phosphorus and arsenic is performed together. However, the disadvantage with the DDD structure is that due to cooperative diffusion effects, phosphorus tends to diffuse faster in the presence of high arsenic doping, even faster than phosphorus diffuses alone. This undesirable effect that enhances the phosphorus diffusion discourages the use of arsenic and phosphorus together in a DDD, and phosphorus alone or GSDs and LDDs are used instead.
Shown in FIG. 2 is a pair of prior art MOSFETs 10 on a semiconductor substrate 12, such as silicon, covered by a thin gate dielectric material 14. It will be appreciated that the substrate 12 may be a well within a wafer or expitaxial layer, or an epitaxial layer itself, and that for PMOS devices the substrate 12 is n-type as shown in the right side of FIG. 1 and for NMOS devices, the substrate 12 is p-type as shown on the left. Upon the thin gate dielectric material 14 is a patterned gate material 15 having opposing sides adjacent which are source/drain regions 16 through 19. It will be appreciated that the source/drain regions 16, and especially n.sup.- and p.sup.- source/drain regions 17 are deeper than desired due to the accelerated phosphorus diffusion of heavily doped phosphorus, and thus these LDDs suffer from the same disadvantages as the graded source/drains with deep junctions discussed above. The same accelerated diffusion phenomenon is observed for boron in the source/drain regions 18 and 19 of the PMOS devices, but to a lesser degree.
A particular need is to provide a workable salicided twin-tub CMOS process. It will be understood that the terms "salicidation" and "silicidation" as used herein refer to the formation of a self-aligned refractory metal silicide on a silicon surface through the reaction of a refractory metal with the silicon surface. The surface may be amorphous, polycrystalline or monocrystalline silicon.
Salicidation of shallow junctions has been shown to result in increased leakage current with can be aggravated by the isolation edge pull back for a LOCOS (local oxidation of silicon) based isolation. Additional source/drain implantation after titanium deposition either before or after silicidation have been proposed to minimize these problems.
However, the high dose phosphorus and boron implants which are performed through the silicide layer to form the n.sup.+ and p.sup.+ regions result in an enhanced diffusivity in the n.sup.- and p.sup.- regions causing anomalously deep source/drain junctions with degraded device punchthrough leakage. This is confirmed by electrical measurements in which an increase in the electrical channel length by 0.15 .mu.m and a corresponding decrease in punchthrough leakage are observed when arsenic is used instead of phosphorus for the n.sup.+ source/drain implant. Due to the high stopping power of arsenic in titanium silicide, high implant energies such as 190 keV are required to see improvements in short-channel effects while maintaining low diode leakage and contact resistance. Evidence exists that such high implant energies tend to adversely shift the threshold voltage of the device, although the reason for this is unknown. The use of arsenic will be limited, therefore, by implantation throughput and potential penetration into the gate oxide. One might argue that arsenic may be employed in a salicided CMOS process by implantation through the silicided layers after the phosphorus has been placed if a thin enough silicide is used. However, such thin silicide layers have the disadvantage of high sheet resistance which is not desired for the circuit speed.
Conventional twin-tub CMOS processes which use low temperature oxide (LTO) sidewall spacers for both the LDD and salicide formation are known. See, for example, U.S. Pat. No. 4,722,909 to Motorola.
Thus, an acceptable process for forming CMOS devices with salicided contacts is desired that does not have these difficulties.